1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of removing gate cap layers in integrated circuit products that employ CMOS technology.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. A gate insulation layer is positioned between the gate electrode and the channel region that will be formed in the substrate. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode exceeds the threshold voltage of the transistor, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when the voltage applied to the gate electrode exceeds the threshold voltage of the transistor, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
Many integrated circuit products are formed using both NFET and PFET devices, i.e., the products are manufactured using so-called CMOS (Complementary Metal Oxide Semiconductor) technology. FIGS. 1A-1D depict one illustrative prior art process flow for forming a semiconductor product or device 10 that includes an illustrative PFET transistor 10P and an illustrative NFET transistor 10N. As shown in FIG. 1A, the process begins with the formation of illustrative gate structures 14 for the PFET transistor 10P and the NFET transistor 10N in and above regions of the substrate 12 that are separated by an illustrative shallow trench isolation structure 13. The gate structures 14 generally include a gate insulation layer 14A and one or more conductive gate electrode layers 14B. A gate cap layer 16, made of a material such as silicon nitride, is formed above the gate structures 14. Also depicted in FIG. 1A is an illustrative sidewall spacer 18, made of a material such as silicon nitride. The gate structures 14 depicted herein are intended to be schematic and representative in nature, as the materials of construction used in the gate structures 14 may be different for the PFET transistor 10P as compared to the NFET transistor 10N, e.g., the PFET transistor 10P may have multiple layers of conductive metal, etc. The gate insulation layer 14A may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, a high-k (k value greater than 7) insulating material, etc. The gate electrode layer 14B may be comprised of one or more layers of conductive materials, such as polysilicon, amorphous silicon, a metal, etc. The structure depicted in FIG. 1A may be formed by performing a variety of known techniques. For example, the layers of material that make up the gate insulation layer 14A, the gate electrode layer 14B and the gate cap layer 16 may be blanket-deposited above the substrate 12 and, thereafter, one or more etching processes are performed through a patterned mask layer (not shown) to define the basic gate structures 14 and gate cap layers 16 depicted in FIG. 1A. The spacers 18 may be formed by performing a conformal deposition process to deposit a layer of spacer material across the device and thereafter performing an anisotropic etching process. In general, the spacers 18 and the gate cap layer 16 act to protect the gate structures 14 of the devices 10P, 10N as processing operations continue. Importantly, at this point in the process flow, the gate cap layers 16 on both the PFET device 10P and the NFET device 10N have the same approximate thickness, e.g., about 40-50 nm, depending upon the particular application.
FIG. 1B depicts the device 10 after several process operations have been performed. Various well-known process operations that are performed to implant various dopant materials for the source/drain regions of the devices 10P, 10N, such as masking and ion implantation processes, will not be depicted or described as they are not particularly germane to the problems with the prior art manufacturing techniques described herein or the solutions discussed herein for such problems. At the point of fabrication depicted in FIG. 1B, one or more ion implantation processes would have been performed on the NFET transistor 10N to form various doped regions (not shown) in the substrate 12. Next, a schematically depicted masking layer 20, such as a photoresist mask or a hard mask material (like silicon nitride), is formed so as to cover the NFET transistor 10N and expose the PFET transistor 10P for further processing. Then, one or more etching processes are performed through the masking layer 20 to define cavities 22 in areas of the substrate 12 where source/drain regions for the PFET transistor 10P will ultimately be formed. The depth and shape of the cavities 22 may vary depending upon the particular application. In one example, the cavities 22 may be formed by performing an initial dry anisotropic etching process and, thereafter, performing a wet etching process. FIG. 1B depicts the device 10 after an epitaxial deposition process is performed to form epitaxial silicon/germanium (SiGe) regions 24 in the cavities 22. In the depicted example, the SiGe regions 24 have an overfill portion that extends above the surface of the substrate 12. The SiGe regions 24 may be formed by performing well-known epitaxial deposition processes.
Importantly, during the process of forming the cavities 22 and the SiGe regions 24, some of the gate cap layer 16 and the spacers 18 on the PFET device 10P are consumed, while the NFET device 10N is protected by the masking layer 20 during such process operations. The consumption of these structures is reflected by the use of the designation 16R for the recessed gate cap layer and the designation 18R for the recessed spacers on the PFET device 10P. The amount of consumption of the original gate cap layer 16 on the PFET device 10 during these process operations may vary depending upon the particular application and the precise process flow. In some cases, the recessed gate cap layer 16R may be approximately one-half of the initial thickness of the original gate cap layer 16. The recessed spacers 18R have also been reduced in thickness and overall height during these process operations, i.e., note the pull-down of the spacers 18R relative to the upper surface of the recessed gate cap layer 16R.
FIG. 1C depicts the device 10 after several process operations have been performed. First, the masking layer 20 was removed. Thereafter, sacrificial sidewall spacers 26 were formed adjacent the spacers 18R, 18. The sacrificial sidewall spacers 26 may be formed by depositing a layer of spacer material, e.g., silicon dioxide, and thereafter performing an anisotropic etching process. Eventually, the gate cap layers 16R, 16 will be removed to expose the gate electrodes 14B so that a metal silicide region may be formed on the gate electrodes 14B. The purpose of the sacrificial sidewall spacers 26 is to protect the relatively thin sidewall spacers 18R, 18 during the gate cap removal process, since the sidewall spacers 18R, 18 are typically made of the same material as that of the gate cap layers 16R, 16, e.g., silicon nitride.
FIG. 1D depicts the device 10 after several process operations have been performed. First, a gate cap etching process was performed to remove the gate cap layers 16R, 16 and expose the underlying gate electrodes 14B for further processing. During this gate cap etching process, the sacrificial sidewall spacers 26 protect the sidewall spacers 18R, 18. Thereafter, another etching process was performed to remove the sacrificial sidewall spacers 26. These process operations result in the structure depicted in FIG. 1D. The gate cap etching process must be performed for a sufficient duration to insure that the thicker gate cap layer 16 on the NFET device 10N is completely removed. Importantly, due to the reduced thickness of the recessed gate cap layer 16R on the PFET device, the gate cap etching process consumes even more of the recessed spacers 18R on the PFET device. The additional consumption of the recessed spacers 18R is reflected by the use of the designation 18X for the spacers on the PFET device 10P. The spacers 18 on the NFET device 10N are also subject to some attack during the gate cap etching process. The size reduction of the recessed spacers 18 on the NFET device 10N is reflected by the use of the designation 18N. However, due to the presence of the thicker gate cap layer 16 on the NFET device 10N, the amount of the spacer material consumed on the NFET device 10N is much less than the amount of the spacer material consumed on the PFET device, as depicted in FIG. 1D. Note that enough of the spacer material on the PFET device 10P has been consumed such that portions of the side surfaces of the gate electrode 14B have been exposed, in the regions indicated by the arrow 30.
A device having the structure depicted in FIG. 1D can be problematic for several reasons. First, the excessive pull-down of the spacers on the PFET device 10P, as reflected by the spacers 18X, can lead to decreased device performance and increased processing instability as the amount of such excessive pull-down may vary from wafer to wafer. The excessive pull-down of the spacer material on the PFET device 10P may result in undesirable dopants being implanted into the channel region of the PFET device 10P due to the exposed sidewalls of the gate electrode 14B, e.g., dopants used for so-called halo implants may be unintentionally implanted into the channel region of the PFET device 10P. Another problem may occur when forming metal silicide regions on the gate electrodes 14B. Ideally, the metal silicide region on the gate electrodes will only be formed on the top surface of the gate electrodes 14B. Thus, the gate electrode 14B for the NFET device 10N reflects the ideal condition for beginning the silicidation process, i.e., only the upper surface of the gate electrode is exposed. In contrast, due to the excessive consumption of the spacer material for the PFET device 10P, and the resulting exposure of the sidewalls of the gate electrode 14B for the PFET device 10P, the metal silicide material will form on the top of the gate electrode and, at least to some extent, on the exposed sidewalls of the gate electrode for the PFET device 10P. Creating such a relative large region of silicide material in a region where it is not expected to be may lead to reduced device performance and/or complete failure due to electrical shorts.
The present disclosure is directed to various novel methods of removing gate cap layers in integrated circuit products that employ CMOS technology that may avoid, or at least reduce, the effects of one or more of the problems identified above.